The present invention relates to frequency compensation of multi-stage amplifier circuits. Particularly, but not exclusively, the invention provides a frequency compensating scheme for negative feedback amplifier circuits such as voltage regulators, and in particular for low drop-out voltage regulators.
Multi-stage amplifier circuits (which may be integrated on a single chip) are used in many applications. One such common application is power supply voltage regulators which are universally used to convert an unregulated DC input voltage to a regulated DC output voltage using negative feedback to compare the output voltage with a stable reference voltage. A typical voltage regulator comprises a transistor output stage controlled by a differential amplifier (the error amplifier). The output of the error amplifier is coupled to the base/gate of the output transistor and thus controls the voltage at the base/gate. The output stage receives an unregulated DC input and delivers a regulated DC output voltage which is controlled by negative feedback to an input of the error amplifier, the other input of the amplifier being coupled to a stable voltage reference. In a regulator which produces an output voltage greater than the reference voltage, a voltage divider couples the output port to ground and the negative feedback signal is developed at a node located within the voltage divider so that a fraction of the output voltage is compared with the reference voltage and the output voltage is maintained at a predetermined multiple of the reference voltage.
The efficiency of a voltage regulator can be increased by minimizing the drop-out voltage (i.e. the voltage difference between the unregulated input voltage and the regulated output voltage). Conventionally this is achieved by operating the output pass transistor in common source/emitter mode using, for instance, a pnp transistor or, more commonly, a P-MOSFET (which will produce a positive polarity output). Such voltage regulators are referred to as low drop-out voltage regulators (LDO regulators).
A disadvantage of conventional LDO regulators is that they are highly sensitive to loading conditions (i.e. output current and capacitance) and must be frequency compensated in order to ensure the output voltage remains stable. Conventional frequency compensation schemes limit the load regulation performance and DC accuracy of the output.
Accordingly, it is a first object of the present invention to provide an amplifier circuit with improved frequency compensation.
A further problem associated with many conventional frequency compensation methods is the injection of ripple into the output voltage. It is desirable to reduce this as much as possible. This may be achieved by the addition of a large bypass capacitor to the output or by the use of cascode compensation. It is, however, a further object of the present invention to provide a scheme for improved supply ripple rejection in an amplifier circuit.
According to a first aspect of the present invention there is provided an amplifier circuit comprising a first amplifier stage controlling a second gain stage which is coupled between an input node and an output node, and a frequency compensating circuit coupled between a compensating circuit node of the second gain stage and a control input of the second gain stage, wherein the output stage comprises:
first and second output devices arranged such that for a given gate voltage, the output current from the first device is greater than the output current from the second device;
the output devices having a common source coupled to the input node and a common gate, which constitutes said control input, coupled to the first amplifier stage;
the drain of the first output device being coupled to the output node and the drain of the second output device being coupled to the compensating circuit node; and
a resistance device connected between the drains of the two output devices.
According to a second aspect of the present invention there is provided a frequency compensating circuit for an amplifier circuit which comprises an output device coupled between an input node and an output node and controlled by an amplifier stage, the source of the output device being coupled to the input node, the drain of the output device being coupled to the output node, and the gate of the output device being coupled to the amplifier, the frequency compensating circuit comprising:
a second output device having its source coupled to the input node and its gate coupled to the output of the amplifier stage in common with the first output device; and
a capacitor coupled between the drain of the second output device and the common gate of the first and second output devices;
wherein the second output device is configured to produce a smaller current than the first output device for a given gate voltage, and the drains of the first and second output devices are separated by a resistance device.
It is to be understood that although the terms gate, source and drain have been used above (and in the appended claims), the invention is not limited to FET devices and could be implemented using other devices such as bipolar transistors and valves. Accordingly, the terms xe2x80x9cgatexe2x80x9d, xe2x80x9csourcexe2x80x9d and xe2x80x9cdrainxe2x80x9d should be interpreted as covering the corresponding elements of other forms of output device such as, for instance, the base, emitter and collector of a transistor.
It will be appreciated that the resistance device may be any device which has resistance and need not be a conventional resistor. For instance, the resistance could be provided by a transistor. The value of the resistance may vary considerably with different applications of the invention and can be selected as appropriate for any given application. For example, in a typical voltage regulator an appropriate resistance may be in the range of 1 kxcexa9 to 20 kxcexa9 although for other amplifier circuits the appropriate resistance may be much higher or much lower than this range.
Reference is made to a compensating circuit coupled between a compensating node and a control input of the second gain stage. It is to be understood that the compensation circuit need not necessarily be coupled directly to either the compensating node or the control input and there may be other circuit elements which interconnect the compensating circuit with the compensating circuit node and/or second gain stage input.
Preferably the first and second output devices are arranged to provide a fixed ratio of output currents over the operational range of the amplifier circuit. The ratio of the two currents may vary significantly in different embodiments of the invention. The invention will operate at any ratio greater than 1:1 and the ratio could be many thousands to 1. In many practical applications the ratio will be of the order of at least 1000:1.
The present invention has many applications and in particular is suitable for frequency compensating LDO voltage regulators.
Other alternative and preferred features of the invention will be apparent from the following description and the appended claims.